PCB design checklist
- Check board size with packaging ''first''
- Put all components interacting with casing on a 0.5 mm grid with regards
to the package outline, not the center
- Mounting holes for components and board itself
- Screw holes: 3.2mm: library
- Ground plane / shielding frame?
- Copper-free border for sawing and mounting?
- Unused I/O to debugging / add-on connector?
- Test pins for signals?
- Add series resistors to "real" test interfaces against short circuits
- 180R @ 5V: 27mA
- 120R @ 5V: 42mA
- 180R @ 3.3V: 18mA
- 120R @ 3.3V: 28mA
- Power connector pins (at least GND) for testing/measurements?
- 0R resistors (or wire bridges) on power supply lines for current
- Use the net naming conventions.
- Do not use the
Vcc net, use
PP_* supply nets instead. An allowable
exception may be schematics using only a single supply voltage, but still,
this is not advised.
- To prevent something from showing up in BOM, add attribute "NOSTUFF".
- All markings vector font, "ratio" 10%.
- Documentation in schematic
- Section titles vector font, size 200 mil, ratio 8%
- All other text vector font, size 70 mil, ratio 8%
- Markings on PCB:
- Layer tPlace:
- 70 mil:
- 50 mil:
Modular CAN-I/O, Bus Logic Board
- 50 mil: All part and value designators
- 50 mil: All other text and documentation
- 16 mil: Line width for "important" separators
- 10 mil: Line width for part placement drawings
- 7 mil: line width for lines from designators to parts
- On boards stuffed on both sides, include "top" and "bot" in size 50mil
on tPlace and bPlace, respectively, near the part designator text.
- Via drills sizes (verification required on actual board layout!)
- track width <= 15 mil: 0.5 mm drill
- track width >= 40 mil: 0.6 mm drill
- track width > 60 mil: use multiple (2-3) vias of 0.6 mm drill
- Run ERC
- Display all layers for the design rule checks
- Run DRC with manufacturer's design rules
- Run DRC with
- Name and value vector font, text size 70 mil, ratio 8%
- ELOINV attribute vector font, text size 40 mil, ratio 8%, layer Info
- Always make supply pins visible, no implicit connections to invisble nets
- Name and value vector font, text size 50 mil, ratio 10%
- Line width: 10 mil
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